1. Field of the Invention
The present invention relates to a microcomputer embedding an electrically erasable, CPU writable flash memory.
2. Description of Related Art
FIG. 8 is a block diagram showing a configuration of a conventional microcomputer. In this figure, the reference numeral 100 designates a microcomputer, 200 designates a personal computer for transferring programs to the microcomputer 100, and 300 designates an interface circuit for connecting the microcomputer 100 with the personal computer 200. The microcomputer 100 includes a central processing unit (called CPU from now on) 110 for controlling the microcomputer 100 in its entirety, a flash memory 120 for storing programs and the like, a flash memory controller 130 for controlling reading and writing of the flash memory 120, a clock generator 140 for generating internal clock signals of the microcomputer 100, a watchdog timer 150 for detecting runaway of the microcomputer 100, peripheral circuits 160 such as A/D converters or a timer, an interrupt controller 170 for controlling priority of interrupts and the like, and a RAM 180 for temporarily storing the data. The internal circuits of the microcomputer 100 are electrically interconnected by a bus 190. Outside the microcomputer 100, there is connected an oscillator 141 for generating a fundamental oscillation signal of the clock generator 140.
The flash memory controller 130 includes a write/erasing controller 131 for controlling writing and erasing of the flash memory 120, a control register 132 for storing data used for controlling the flash memory, and a command register 133 for storing commands transferred from the CPU to instruct writing/erasing.
Next, the operation will be described.
The clock generator 140 supplies the CPU 110, watchdog timer 150 and peripheral circuits 160 with clock signals CL1, CL2 and CL3, respectively, on the basis of the oscillation frequency of the oscillator 141. The CPU 110 controls the peripheral circuits 160 and others in accordance with the programs stored in the flash memory 120. The watchdog timer 150 always counts the clock signal CL2 generated by the clock generator 140, and outputs an overflow signal OF at every fixed interval T1. Normally, since the CPU 110 sets the watchdog timer 150 at intervals shorter than the fixed interval T1, the overflow signal OF is not output. On the contrary, if the CPU 110 does not set the watchdog timer 150 within an interval shorter than the fixed interval T1 because of an abnormal operation of the CPU 110 or the like, the interrupt controller 170 carries out the interrupt priority processing so that an interrupt signal INT is sent to the CPU 110 to cause an interrupt to the CPU 110, and the CPU 110 executes an abnormal processing program.
Next, the operation of writing data, which is transferred from the personal computer 200, to the flash memory 120 in the microcomputer 100 will be described. The flash memory 120 stores a program for writing the externally supplied data into the flash memory 120 itself. FIG. 9 is a flowchart illustrating the operation of the CPU 110 in the write operation.
When the CPU 110 is started in a CPU rewrite mode set by external dip switches or the like, the CPU 110 transfers a data rewrite program stored in the flash memory 120 to the RAM 180 at step ST901 so that the CPU 110 operates in accordance with the program transferred to the RAM 180. Next, the CPU 110 designates the CPU rewrite mode at step ST902 by writing "1" into a bit in the control register 132, which bit specifies the CPU rewrite mode. Then, the CPU rewrite mode specifying signal M from the control register 132 is fed to the write/erasing controller 131. This causes the write/erasing controller 131 to wait for a command to be written into the command register 133 by the CPU 110 to execute it.
When the CPU 110 writes the write command into the command register 133, the write/erasing controller 131 decodes the command, and identifies that it is the write command into the flash memory 120. Subsequently, the CPU 110 receives the data to be written into the flash memory 120 from the personal computer 200 through the interface circuit 300, and transfers the data to the flash memory 120 at step ST903. The write/erasing controller 131 generates a write pulse WP to carry out writing of the data into the flash memory 120. The writing is implemented when the write pulse WP is "1" which is turned off to "0" when the writing has been completed. Erasing of the data can be implemented by generating similar pulses.
The CPU 110 reads through the control register 132 the busy signal BSY indicating that the write processing is in progress at step ST504, and when the busy signal falls to "0" at step ST905, it checks at step ST906 whether the data are written correctly into the flash memory 120 or not. If it is found at step ST907 as a result of the check that the data transfer includes some error, the CPU 110 retransmits the same data at step ST908. On the contrary, if it is decided at step ST907 that the data transfer has been completed correctly, the CPU 110 sets watchdog timer 150 at step ST909, and checks at step ST910 whether an intended amount of data has been written. If it has been written, the CPU 110 clears the CPU rewrite mode at step ST911, and completes the operation.
The erasure of the flash memory 120 can also be implemented in a manner similar to the write operation described above by writing "1" into a bit in the control register 132, which indicates the CPU rewrite mode, and then by writing the erasing command in the command register 133.
In the conventional microcomputer there are following problems: First, since a time period taken by the write/erasing operation is usually longer than a normal microcomputer operation time, the watchdog timer 150 often overflows during the write/erasing operation, which causes an abnormal interrupt. Second, the software is overloaded to carry out time management for setting the watchdog timer 150 so that the watchdog timer 150 does not overflow even if the write/erasing operation takes a long time.
Thus, the conventional microcomputer including a flash memory has a problem in that the software is overloaded when the CPU controls the set of the watchdog timer 150.